The development of science and technology has put forward increasingly higher requirements for chip designing and manufacturing. A system on chip (SoC), which is technically supported by adopting IP core reuse and software/hardware co-verification thereof, has become the mainstream method for designing high performance integrated circuits. It has also been evolved into a huge system engineering from the chip system definition, front-end circuit design, back-end physical implementation, chip manufacturing, packing and testing to software development and then to the final mass production. At present, the mainstream chips are still ASIC and FPGA chips.
The ASIC is an integrated circuit designed and manufactured in response to the requirements of a specific user and the needs of a specific electronic system. Compared with a general integrated circuit, the ASIC in batch production has the advantages of small size and low power consumption, but the ASIC is not a reconfigurable chip, has a longer time to market, and also needs tape-out. The expense for one-time tape-out is very high, and the cost can be reduced only in the case of large amount.
The FPGA is based on the ASIC, and its basic principle is to use an LUT (Lookup Table). The LUT is essentially a memory table. Data is written into the memory table in advance. When a signal is inputted in each time, it is equivalent to entering an address to look up the table to find contents corresponding to the address, and then output the contents. The FPGA allows the chip structure to be reconfigured in a static state, and even be reconfigured in a locally dynamic state. The FPGA has an obvious advantage over the ASIC on the time-to-market; however, a designed circuit still needs to be written into the chip in general. The application cost of the FPGA for a small quantity is relatively low, but is relatively high for a large quantity.
The ASIC has fixity. Once the ASIC is completely designed, the chip functions thereof are fixed. Unless the chip is damaged, the functions of the ASIC will not be changed. This chip can only adapt to a specific function, but cannot change with different requirements, and it is basically impossible to update hardware. If the chip is designed for a satellite, once the satellite arrives in space, it will cost a lot to upgrade the hardware.
Although the FPGA corporation may provide some configurable chips, because the way of look-up table is used, it is necessary to calculate all the possible data before writing data into the chip, and then write the huge data to each lookup table. In this way, as the configuration data increases, the time for writing the data into the FPGA will be longer and longer. Even if local reconfiguration is possible, the FPGA cannot be reconfigured at a super-fast speed because the reconfiguration speed is greatly limited due to the huge amount of the configured data.
With the increase of the chip scale and design complexity, the reconfiguration time of the chip is becoming longer and longer. It is very difficult to use the existing FPGA technology to realize dynamic real-time reconstruction.
Therefore, it is necessary to design a self-adaptive chip that can realize the dynamic reconfiguration function and realize the function of multi-purpose for one-chip.
The above information disclosed in the background section is only for enhancement of understanding the background of the disclosure and therefore it may contain information that does not form the prior art that is already known to those having ordinary skills in the art.